1. Field of the Invention
The present invention relates to circuits and method of input/output impedance control of semiconductor devices.
2. Description of the Related Art
Impedance matching between a semiconductor device and a transmission line has become increasingly important in high-speed interfacing such as SerDes (“serializer/deserializer”) due to the recent increase in the operating speed of the semiconductor device.
One conventional approach is to use a transistor or a resistor integrated within a semiconductor device as a terminating resistor. However, terminating resistors composed of a transistor or a resistor integrated within a semiconductor device suffer from fluctuations and/or variations of the resistance thereof, due to the manufacturing variations, power supply voltage fluctuations, and temperature fluctuations. The fluctuations and variations of the resistances of terminating resistors undesirably cause impedance mismatch between a semiconductor device and a transmission line connected to the semiconductor device, resulting in undesirable signal reflection. This undesirably restricts the maximum operating frequency of the semiconductor device and the maximum signal transmission distance.
One approach for solving the above-described problem is to integrate an impedance control circuit that achieves impedance matching through controlling an output impedance of a driver and/or an input impedance of a receiver.
Japanese Laid-Open Patent Application No. Jp-A 2001-94409 discloses an impedance control circuit for controlling an output impedance of an output buffer. The disclosed impedance control circuit is composed of NMOS and PMOS transistor arrays each having a controllable impedance, first and second counters, first and second comparators. The first comparator compares a voltage developed across the NMOS transistor array with a reference voltage generated by voltage dividing using serially connected external transistors. The first counter is counted up in response to the output of the first comparator. The counter value of the first counter is fed to the NMOS transistor array and used for controlling the impedance of the NMOS transistor array. Correspondingly, the second comparator compares a voltage developed across the PMOS transistor array with the reference voltage. The second counter is counted up in response to the output of the second comparator. The counter value of the second counter is fed to the PMOS transistor array and used for controlling the impedance of the PMOS transistor array. The number of activated pull-down transistors within the output buffer is controlled in response to the counter value of the first counter, while the number of activated pull-up transistors within the output buffer is controlled in response to the counter value of the second counter. This achieves improved impedance control of the output buffer.
Japanese Laid-Open Patent application No. Jp-A 2005-26890 discloses a similar impedance control circuit that additionally includes an NMOS arbitration circuit, and a PMOS arbitration circuit. The NMOS arbitration circuit detects the output level of the first comparator for each counter value of the first counter three times or more, and performs majority operation on the detected output levels. The NMOS arbitration circuit allows the first counter to be counted up or down on the basis of the result of the majority operation. The PMOS arbitration circuit operates correspondingly to allow the second counter to be counted up or down.
Japanese Laid-Open Patent Application No. Jp-A 2004-32721 discloses an impedance control circuit for generating a thermometer code used for impedance control. In this impedance control circuit, a comparator compares a voltage generated by voltage dividing using an impedance-controllable circuit with a reference voltage. The output signal of the comparator is fed to an up-down counter, and used for controlling the counting up or down of the counter. The impedance of the impedance-controllable circuit is controlled in response to the counter value of the up-down counter. The counter value of the up-down counter is also fed to an averaging circuit, and the thermometer code is generated in response to the output of the averaging circuit. The averaging circuit is composed of a set of synchronization circuits and adder circuits.
FIG. 1 illustrates an exemplary structure of a typical conventional impedance system 1. An external reference resistor 9 having a highly accurate resistance is connected to a pad 8 and a power supply terminal 10. A comparator 5 compares a voltage generated through voltage dividing by the external reference resistance 9 and a replica circuit 7 with a desired reference voltage. The replica circuit 7 is a replica of target circuits 6a and 6b. The output signal of the comparator 5 is inputted to an n-bit up-down counter 4. The up-down counter 4 is counted up or down in response to the output signal of the comparator 5, in synchronization with a clock signal 14. The up-down counter 4 generates an impedance control code 12 indicative of the counter value of the up-down counter 4, and provides the impedance control code 12 to the replica circuit 7. Thee resistance across the replica circuit 7 is controlled in response to the impedance control code 12. The impedance control code 12 is also fed to an anti-dithering circuit 3. The anti-dithering circuit 3 generates an anti-dithering impedance control code 13, and provides the anti-dithering impedance control code 13 for the target circuits 6a and 6b. The comparator 5, the up-down counter 4, and the replica circuit 7 provides a closed loop used for controlling the impedances of the target circuits 6a and 6b. 
The conventional impedance control system 1, however, suffers from several problems.
A first problem is that the impedances of the target circuits 6a and 6b may be inaccurately controlled when the system 1 is subjected to a large power source noise or a large switching noise generated by other digital circuits. This problem may be been caused, because the comparator 5 continuously performs the comparison operation, and the impedance control code 12, which is fed to the replica circuit 7, is responsive to the comparison result of the comparator 5. When the comparator 5 receives a transient voltage noise at an input thereof, the output signal of the comparator 5 may be erroneously flipped. This may result in the impedance control code 12 is erroneously generated.
A second problem is that a non-binary code such as a thermometric code is necessarily used as the impedance control code 12 in order to avoid data transmission errors. This undesirably increases the circuit size and o the number of control signals within the impedance control system 1. This is because the use of a binary code is accompanied by impedance discontinuity when the impedance control code 12 is updated, considerably deteriorating the waveform of transmission signals. In the impedance control system 1, the impedance control code 12 is continuously updated by the closed loop, and the update of the impedance control code 12 is not synchronous with the data transmission.